circuit MYAccumulator :
  module MYAccumulator :
    input clock : Clock
    input reset : UInt<1>
    output io : { accumIO : { flip dataIn : SInt<32>, flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip raddr : UInt<8>, flip lastvec : UInt<1>, dataOut : SInt<32>, waddrDelay : UInt<8>, wenDelay : UInt<1>, wclearDelay : UInt<1>, lastvecDelay : UInt<1>}}

    smem mem : SInt<32> [256] @[Accumulator.scala 31:30]
    when io.accumIO.wen : @[Accumulator.scala 33:29]
      when io.accumIO.wclear : @[Accumulator.scala 34:40]
        write mport MPORT = mem[io.accumIO.waddr], clock
        MPORT <= io.accumIO.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 37:81]
        _WIRE is invalid @[Accumulator.scala 37:81]
        when UInt<1>("h1") : @[Accumulator.scala 37:81]
          _WIRE <= io.accumIO.waddr @[Accumulator.scala 37:81]
          node _T = or(_WIRE, UInt<8>("h0")) @[Accumulator.scala 37:81]
          node _T_1 = bits(_T, 7, 0) @[Accumulator.scala 37:81]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 37:81]
        node _T_2 = add(io.accumIO.dataIn, MPORT_1) @[Accumulator.scala 37:71]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 37:71]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 37:71]
        write mport MPORT_2 = mem[io.accumIO.waddr], clock
        MPORT_2 <= _T_4
    wire _io_accumIO_dataOut_WIRE : UInt @[Accumulator.scala 41:39]
    _io_accumIO_dataOut_WIRE is invalid @[Accumulator.scala 41:39]
    when UInt<1>("h1") : @[Accumulator.scala 41:39]
      _io_accumIO_dataOut_WIRE <= io.accumIO.raddr @[Accumulator.scala 41:39]
      node _io_accumIO_dataOut_T = or(_io_accumIO_dataOut_WIRE, UInt<8>("h0")) @[Accumulator.scala 41:39]
      node _io_accumIO_dataOut_T_1 = bits(_io_accumIO_dataOut_T, 7, 0) @[Accumulator.scala 41:39]
      read mport io_accumIO_dataOut_MPORT = mem[_io_accumIO_dataOut_T_1], clock @[Accumulator.scala 41:39]
    io.accumIO.dataOut <= io_accumIO_dataOut_MPORT @[Accumulator.scala 41:28]
    reg io_accumIO_waddrDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 43:41]
    io_accumIO_waddrDelay_REG <= io.accumIO.waddr @[Accumulator.scala 43:41]
    io.accumIO.waddrDelay <= io_accumIO_waddrDelay_REG @[Accumulator.scala 43:31]
    reg io_accumIO_wenDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 44:41]
    io_accumIO_wenDelay_REG <= io.accumIO.wen @[Accumulator.scala 44:41]
    io.accumIO.wenDelay <= io_accumIO_wenDelay_REG @[Accumulator.scala 44:31]
    reg io_accumIO_wclearDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 45:41]
    io_accumIO_wclearDelay_REG <= io.accumIO.wclear @[Accumulator.scala 45:41]
    io.accumIO.wclearDelay <= io_accumIO_wclearDelay_REG @[Accumulator.scala 45:31]
    reg io_accumIO_lastvecDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 46:42]
    io_accumIO_lastvecDelay_REG <= io.accumIO.lastvec @[Accumulator.scala 46:42]
    io.accumIO.lastvecDelay <= io_accumIO_lastvecDelay_REG @[Accumulator.scala 46:32]

